This application is related to the following co-pending and commonly-assigned patent applications, which applications were filed on the same. date herewith, and which applications are incorporated herein by reference in their entirety:
xe2x80x9cMethod and System for Multiple Read/Write Transactions Across a Bridge System,xe2x80x9d to Gary W. Batchelor, Russell L. Ellison, Carl E. Jones, Robert E. Medlin, Belayneh Tafesse, Forrest Lee Wade, and Juan A. Yanes, Ser. No. 09/275,470;
xe2x80x9cMethod And System For Prefetching Data in a Bridge System,xe2x80x9d to Gary W. Batchelor, Carl E. Jones, Forrest Lee Wade, Ser. No. 09/275,857; and
xe2x80x9cMethod And System For Reading Prefetched Data Across a Bridge System,xe2x80x9d to Gary W. Batchelor, Brent C. Beardsley, Matthew J. Kalos,. and Forrest Lee Wade, Ser. No. 09/275,610.
1. Field of the Invention
The present invention relates to a method and system for prefetching data within a bridge system.
2. Description of the Related Art
The Peripheral Component Interconnect (PCI) bus is a high-performance expansion bus architecture that was designed to replace the traditional ISA (Industry Standard Architecture) bus. A processor bus master communicates with the PCI local bus and devices connected thereto via a PCI Bridge. This bridge provides a low latency path through which the processor may directly access PCI devices mapped anywhere in the memory or I/O address space. The bridge may optionally include such functions as data buffering/posting and PCI central functions such as arbitration. The architecture and operation of the PCI local bus is described in xe2x80x9cPCI Local Bus Specification,xe2x80x9d Revisions 2.0 (April, 1993) and Revision 2.1s, published by the PCI Special Interest Group, 5200 Elam Young Parkway, Hillsboro, Oreg., which publication is incorporated herein by reference in its entirety.
A PCI to PCI bridge provides a connection path between two independent PCI local busses. The primary function of the bridge is to allow transactions between a master on one PCI bus and a target device on another PCI bus. The PCI Special Interest Group has published a specification on the architecture of a PCI to PCI bridge in xe2x80x9cPCI to PCI Bridge Architecture Specification,xe2x80x9d Revision 1.0 (Apr. 10, 1994), which publication is incorporated herein by reference in its entirety. This specification defines the following terms and definitions:
initiating busxe2x80x94the master of a transaction that crosses a PCI to PCI bridge is said to reside on the initiating bus.
target busxe2x80x94the target of a transaction that crosses a PCI to PCI bridge is said to reside on the target bus.
primary interfacexe2x80x94the PCI interface of the PCI to PCI bridge that is connected to the PCI bus closest to the CPU is referred to as the primary PCI interface.
secondary interfacexe2x80x94the PCI interface of the PCI to PCI bridge that is connected to the PCI bus farthest from the CPU is referred to as the secondary PCI interface.
downstreamxe2x80x94transactions that are forwarded from the primary interface to the secondary interface of a PCI to PCI bridge are said to be flowing downstream.
upstreamxe2x80x94transactions forwarded from the secondary interface to the primary interface of a PCI to PCI bridge are said to be flowing upstream.
The basic transfer mechanism on a PCI bus is a burst. A burst is comprised of an address phase and one or more data phases. When a master or agent initiates a transaction, each potential bridge xe2x80x9csnoopsxe2x80x9d or reads the address of the requested transaction to determine if the address is within the range of addresses handled by the bridge. If the bridge determines that the requested transaction is within the bridge""s address range, then the bridge asserts a DIESEL# on the bus to claim access to the transaction.
There are two types of write transactions, posted and non-posted. Posting means that the write transaction is captured by an intermediate agent, such as a PCI bridge, so that the transaction completes at the originating agent before it completes at the intended destination, e.g., the data is written to the target device. This allows the originating agent to proceed with the next transaction while the requested transaction is working its way to the ultimate destination. Thus, the master bus initiating a write operation may proceed to another transaction before the written data reaches the target recipient. Non-posted transactions reach their ultimate destination before completing at the originating device. With non-posted transactions, the master cannot proceed with other work until the transaction has completed at the ultimate destination.
All transactions that must complete on the destination bus, i.e., secondary bus, before completing on the primary bus may be completed as delayed transactions. With a delayed transaction, the master generates a transaction on the primary bus, which the bridge decodes. The bridge then ascertains the information needed to complete the request and terminates the request with a retry command back to the master. After receiving the retry, the master reissues the request until it completes. The bridge then completes the delayed read or write request at the target device, receives a delayed completion status from the target device, and returns the delayed completion status to the master that the request was completed. A PCI to PCI bridge may handle multiple delayed transactions.
With a delayed read request, the read request from the master is posted into a delayed transaction queue in the PCI to PCI bridge. The bridge uses the request to perform a read transaction on the target PCI bus and places the read data in its read data queue. When the master retries the operation, the PCI to PCI bridge satisfies the request for read data with data from its read data queue.
With a delayed write request, the PCI to PCI bridge captures both the address and the first word of data from the bus and terminates the request with a retry. The bridge then uses this information to write the word to the target on the target bus. After the write to the target has been completed when the master retries the write, the bridge will signal that it accepts the data with TRDY# thereby notifying the master that the write has completed.
The PCI specification provides that a certain ordering of operations must be preserved on bridges that handle multiple operations to prevent deadlock. These rules are on a per agent basis. Thus, for a particular agent communicating on a bus and across a PCI bridge, the agent""s reads should not pass their writes and a later posted write should not pass an earlier write. However, with current bridge architecture, only a single agent can communicate through the PCI bridge architecture at a time. If the PCI bridge is handling a delayed request operation and a request from another agent is attempted, then the PCI bridge will terminate the subsequent transaction from another agent with a retry command. Thus, a write operation from one agent that is delayed may delay read and write operations from other agents that communicate on the same bus and PCI bridge. Such delays are referred to as latency problems as one agent can delay the processing of transactions from other agents until the agent currently controlling the bus completes its operations. Further, with a delayed read request, a delayed read request from one agent must be completed before other agents can assert their delayed read requests.
Current systems attempt to achieve a balance between the desire for low latency between agents and high throughput for any given agent. High throughput is achieved by allowing longer burst transfers, i.e., the time an agent or master is on the bus. However, increasing burst transfers to improve throughput also increases latency because other agents must wait for the agent currently using the longer bursting to complete. Current systems employ a latency timer which is a clock that limits the amount of time any one agent can function as a master and control access to the bus. After the latency time expires, the master may be required to terminate its operation on the bus to allow another master agent to assert its transaction on the bus. In other words, the latency timer represents a minimum number of clocks guaranteed to the master. Although such a latency timer places an upper bound on latency, the timer may prematurely terminate a master""s tenure on the bus before the transaction terminates, thereby providing an upper bound on throughput.
One current method for reducing latency is the prefetch operation. Prefetch refers to the situation where a PCI bridge reads data from a target device in anticipation that the master agent will need the data. Prefetching reduces the latency of a burst read transaction because the bridge returns the data before the master actually requests the data, thereby reducing the time the master agent controls access to the bus to complete its requested operation. A prefetchable read transaction may be comprised of multiple prefetchable transactions. A prefetchable transaction will occur if the read request is a memory read within the prefetchable space, a memory read line, and memory read multiple. The amount of data prefetched depends on the type of transaction and the amount of free buffer space to buffer prefetched data.
Disconnect refers to a termination requested with or after data was transferred on the initial data phase when the target is unable to respond within the target subsequent latency requirement and, therefore, is temporarily unable to continue bursting. A disconnect may occur because the burst crosses a resource boundary or a resource conflict occurs. Disconnect differs from retry in that retry is always on the initial data phase, and no data transfers. Disconnect may also occur on the initial data phase because the target is not capable of doing a burst. In current PCI art, if a read is disconnected and another agent issues an intervening read request, then any prefetched data maintained in the PCI buffer for the disconnected agent is discarded. Thus, when the read disconnected agent retries the read request, the PCI bridge will have to again prefetch the data because any prefetched data that was not previously returned to the agent prior to the disconnect would have been discarded as a result of the intervening read request from another agent.
There is thus a need in the art for an improved bridge architecture to handle read/write transactions across a bridge from multiple agents.
Furthermore, the amount of data prefetched from a target and stored in the PCI buffer may be less than the maximum amount of data that is permitted to be transmitted in a burst. If so, transmitting a sub-burst sized block of prefetched data from the PCI buffer to the requesting agent over the primary bus can result in inefficient utilization of the primary bus. Thus, heavy traffic on the secondary bus which cuts short prefetching of data to the PCI buffer can cause the transmission of sub-burst sized blocks of prefetched data over the primary bus and a corresponding increase of traffic on the primary bus. A similar problem is caused by the transmission of sub-burst sized blocks of data in write operations through the PCI bridge.
Provided is an improved bridge system and method for gathering read data to return to a read request from an agent. In the illustrated embodiment, continuous read data obtained from a target device in a number of separate read operations over one bus may be gathered by the bridge and assembled into a larger block of data before forwarding the data over another bus to the requesting agent. As a consequence, the transmission of more optimal bursts of read data over the other bus may be increased.
The bridge system of the illustrated embodiment includes a plurality of read data gathering buffers in which each agent is assigned a particular read data gathering buffer. As a consequence, read data may be concurrently gathered in the separate buffers for more than one agent at a time. In addition the assertion of a read or write request by one agent need not cause the flushing of the data being gathered for a different agent in a separate buffer.
In another feature of the present invention, read data is gathered until an address boundary is crossed. In a preferred embodiment, read data is gathered by a local bridge until the address of the read data reaches a predefined address boundary which may be programmed by storing the value of that address boundary in a register. Once a boundary is reached, the gathered data is forwarded to a remote bridge which forwards the gathered data to the requesting agent. The local bridge then resumes gathering read data from boundary to boundary, forwarding the fetched data between adjacent address boundaries to the requesting agent until all of the data requested by the agent has been fetched and forwarded. It is believed that large amounts of data are more efficiently transmitted and stored when sent in blocks of data having beginning and ending addresses which are aligned with respect to predefined address boundaries.
Also provided is an improved bridge system and method for gathering write data in response to multiple write requests from an agent before forwarding the collected write data to the selected target device. In the illustrated embodiment, write data may be gathered from several write operations over one bus and assembled into an address boundary-aligned block of write data before the bridge circuit forwards the write data to the target device over another bus.